1. Field of the Invention
The present invention relates to the field of semiconductor wafer processing and, more particularly, to a technique for fabricating a dual damascene interconnect structure in which low dielectric constant dielectric layers are used for the inter-level dielectric.
2. Background of the Related Art
In the manufacture of devices on a semiconductor wafer, it is now the practice to fabricate multiple levels of conductive (typically metal) layers above a substrate. The multiple metallization layers are employed in order to accommodate higher densities as device dimensions shrink well below one micron design rules. Likewise, the size of interconnect structures will also need to shrink, in order to accommodate the smaller dimensions. Thus, as integrated circuit technology advances into the sub- 0.25 micron range, more advanced interconnect architecture and new materials are required.
One such architecture is a dual damascene integration scheme in which a dual damascene structure is employed. The dual damascene process offers an advantage in process simplification by reducing the process steps required to form the vias and trenches for a given metallization level. The openings, for the wiring of a metallization level and the underlying via connecting the wiring to a lower metallization level, are formed at the same time. The procedure provides an advantage in lithography and allows for improved critical dimension control. Subsequently, both the via and the trench can be filled utilizing the same metal-filling step, thereby reducing the number of processing steps required. Because of the simplicity of the dual damascene process, newer materials can now cost-effectively replace the use of the existing aluminum/SiO.sub.2 (silicon dioxide) scheme.
One such newer material is copper. The use of copper metallization improves performance and reliability over aluminum, but copper introduces additional problems which are difficult to overcome when using known techniques for aluminum. For example, in conventional aluminum interconnect structures, a barrier layer is usually not required between the aluminum metal line and an SiO.sub.2 inter-level dielectric (ILD). However, when copper is utilized, copper must be encapsulated from the surrounding ILD, since copper diffuses/drifts easily into the adjoining dielectric. Once the copper reaches the silicon substrate, it will significantly degrade the device's performance.
In order to encapsulate copper, a barrier layer of some sort is required to separate the copper from the adjacent material(s). Because copper encapsulation is a necessary step requiring a presence of a barrier material to separate the copper, other materials can now be substituted for the SiO.sub.2 as the material for ILD. Replacing the SiO.sub.2 by a low-dielectric constant (low-.epsilon.) material reduces the interline capacitance, thereby reducing the RC delay, cross-talk noise and power dissipation in the interconnect. However, it is generally necessary to have a barrier (or liner) present between the interconnect and the low-.epsilon. ILD to prevent possible interaction between the interconnect and the low-.epsilon. ILD and also to provide adhesion between them. This barrier is desirable even when aluminum is utilized for the interconnect.
There are generally two types of low-.epsilon. films for integrated circuit applications. One group is comprised of the modified SiO.sub.2 materials, such as fluorinated oxide (add limited F into SiO.sub.2) and silsesquioxane (add limited H or C-based organic elements to SiO.sub.2). The other group is comprised of the organic materials, such as polyimides and polymers, having completely different molecular structures in comparison to SiO.sub.2. One advantage of organic low-.epsilon. films is that they offer a lower dielectric constant than the modified SiO.sub.2 materials.
One known technique of utilizing organic low-.epsilon. dielectric material for damascene interconnect is described in "Planar Copper-Polyimide Back End Of The Line Interconnections For ULSI Devices;" B. Luther et al.; 1993 VMIC Conference; Jun. 8-9, 1993; pp. 15-21. However, the technique described is for a single damascene process. The present invention describes the use of low-.epsilon. dielectric material in a dual damascene process for use as an ILD.